1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. For example, the present invention relates to a structure of a trench MOSFET to be formed on the same substrate as a CMOS and a method of manufacturing the trench MOSFET.
2. Description of the Related Art
MOS transistors are electronic elements playing a central role in electronics. Reducing the size of the MOS transistors and improving the drive performance thereof have been important challenges regardless in a low breakdown voltage region or in a high breakdown voltage region.
A vertical trench MOSFET is often used for applications that require high drive performance since a transistor having a large channel width in a small area can be formed with a trench MOSFET having a vertical structure, in which the movement direction of carriers is set up or down (in a vertical direction) with respect to a semiconductor substrate surface. Trench MOSFETs have been widely used so far as discrete driver elements, but in recent years, there has been proposed a process of integrating the trench MOSFET having high drive performance with a general CMOS transistor forming a control circuit.
The surface shape of the trench MOSFET can be divided into a trench region and a non-trench region when viewed from above. Further, the non-trench region can be divided into a source region as a high concentration impurity region, and a body contact region as a high concentration impurity region for fixing the potential of a body region.
Further, the source region and the body contact region as the non-trench region are generally used at the same potential, and hence both of the impurity regions are arranged adjacent to each other, and are simultaneously connected by the same metal wiring in many cases. In a case of a silicide formation process, both the regions are covered with a continuous silicide, and are connected to a wiring metal in a minimum contact area and number.
In order to improve the drive performance per unit area, it is required to reduce the area of the trench region or the non-trench region. The body contact region, which is a part of the non-trench region, is only required to have a fixed potential. Considering this point, it is effective to set the area of the body contact region small. However, when the potential is unstable, snapback phenomenon occurs in the transistor, which hinders normal operation at a desired operation voltage.
Further, the body contact region is affected by the fluctuations in concentrations of impurities forming the source region and diffusion fluctuations, and hence the body contact region needs to be arranged in an area with more margins. Accordingly, the area cannot be easily reduced.
Conventionally, the source region and the body contact region have been formed by controlling an impurity concentration and heat treatment so that the area can be reduced as much as possible while fixing the potential. Alternatively, as described in Japanese Patent Application Laid-open No. 2002-50760, there has been proposed an idea of providing a position at which the body contact region is arranged and a position at which the body contact region is absent so that the area is reduced as a whole.
In the technology of Japanese Patent Application Laid-open No. 2002-50760, as illustrated in FIG. 5, a trench region 51 and a non-trench region 53 are arranged in a stripe state, and the non-trench region 53 is provided in two types of widths. A body contact region 52 is arranged in a wider part of the non-trench region 53, and the body contact region 52 is not arranged in a narrower part of the non-trench region 53. The adjacent stripes with this arrangement are arrayed in a staggered manner. Thus, the area efficiency is optimized to form the transistor in a minimum area. In this manner, it is intended to reduce the ON resistance of the transistor per unit area.
However, even with the technology of Japanese Patent Application Laid-open No. 2002-50760, the body contact region is required to be arranged in a certain area or more, and this region still restricts the reduction of the transistor area. Further, when the trench regions are arranged in a grid manner, the layout thereof is limited to a stripe state. Further, it cannot be said that the measure of arranging the body contact regions in places is the best method in terms of obtaining uniform transistor characteristics.